Recent years have seen increased high performance in electronic devices such as mobile information devices and information appliances following the development of digital technology. As such, there is an increasing demand for higher-capacity, reduced writing power consumption, increased speed during writing and reading, and extended operational life of nonvolatile storage elements.
In view of these demands, flash memories using existing floating gates have increasingly been miniaturized.
On the other hand, in the case of non-volatile semiconductor storage elements (variable resistance memory) using, for a storage unit, a variable resistance element having a resistance value that is stable when held and changes in response to an application of a voltage pulse, there are expectations for further miniaturization, increased speed, reduced power consumption, and so on, because a memory cell can be simply configured.
PTL 1 discloses a configuration example of a variable resistance element suitable to miniaturization and higher integration. According to the PTL 1, a variable resistance layer and an upper electrode are filled in a via hole formed above a lower electrode. In addition, the upper electrode is convexed toward the variable resistance layer. With the above-described configuration, it is considered that malfunction of the variable resistance element can be reduced.
[Citation List]
[Patent Literature]    [PTL 1]    Japanese Patent No. 4166820